Today Micron Technology announced that it is sampling the Hybrid Memory Cube (HMC) a DRAM packaging technology that it has been working on with the HMC Consortium.
Micron has been pushing to rapidly advance the HMC’s development and seems to have reached this point in an impressively brief time, given the complexity of the technology. It has only been two years since the first public appearance of the HMC at the 2011 Intel Developer Forum.
Some pretty advanced technology was used to make this product. DRAM processes are not very good at high speed signaling, and it has been a real struggle for the industry to provide increasingly-faster interfaces. Since processor speeds race ahead, this has created a bottleneck between the memory and the processor. The HMC uses a dedicated logic chip at the bottom of the stack (the one that sticks out at the bottom of the photo) to drive the bus, so it can achieve significantly faster signalling speeds without burning undue amounts of power.
Another big benefit of this technology is that through-silicon vias (TSVs) connect the DRAM stack with the logic chip. This serves two important purposes: First, it allows the HMC to tap into all the inherent internal parallelism of the DRAM to get very high communication bandwidth. The other is that the DRAM’s I/O drivers for these connections can be very small and low-powered, since they don’t have to drive a much bigger bonding wire. This further reduces the power consumption of the DRAM, compared to alternative high-speed approaches.
Today support exists only on FPGAs from Altera and Xilinx, but Objective Analysis will be carefully watching this technology’s progress, since it should be a good choice as a processor memory.
Initially we anticipate the HMC to find acceptance in network switches, a market that has embraced high-speed/high-price memory solutions like quad data rate (QDR) SRAMs in the past. As production volume increases and manufacturers find ways to drive the costs out of this product it should find more general acceptance.
Over the very long term the HMC is likely to become the DRAM of choice in the majority of computing systems, but that may be a few years out. It is likely to occur when the industry transitions from systems with upgradeable DRAM sizes those with upgradeable NAND on the motherboard, a transition that will occur in the not-too-distant future and one that is explored in our report How PC NAND Will Undermine DRAM. This report can be purchased for immediate download on the Objective Analysis website.
