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In a December 1 press release IBM announced that the company will be manufacturing Micron Technology’s Hybrid Memory Cube (HMC) which IBM claims to be “the first commercial CMOS manufacturing technology to employ through-silicon vias (TSVs).”
This device is one that Altera, Intel, Micron, Open Silicon, Samsung, and Xilinx have all presented recently as a plausible solution to the difficulty of increasing the speed of DRAM/processor communications. The Hybrid Memory Cube Consortium (HMCC) website offers a deep dive into the details of the consortium and the technology.
This is a tough technology to manufacture, but it solves some significant issues. Today’s DRAM chips are burdened with having to drive circuit board traces, connectors, and the I/O pins of numerous other chips to force data down the bus at gigahertz speeds. This is a very difficult job that consumes a lot of energy. The HMC reduces this task to make the DRAM drive only tiny TSVs which are connected to much lower loads over shorter distances. A logic chip at the bottom is the only one burdened with driving the circuit board traces and the processor’s I/O pins. HMCC tells us that this approach increases speed by 15 times while reducing power by 70%.
What is it about HMC technology that’s tough to manufacture? Take a look at what is involved: The interconnect that shows as vertical cylinders in the diagram above is made by drilling holes through the silicon then plugging them with metal – typically titanium and more recently copper. This is a challenge that has only been addressed in very low unit volumes so far. To make this work the DRAM chips must be ground extremely thin which is, in itself, a challenge. Finally, any package that involves multiple chips will have multiple opportunities for a single chip failure that will ruin the entire stack. In an 4-DRAM stack, with one logic chip at the bottom, like the one in the illustration, any failed chip will prevent the others from being used, so the entire assembly will need to be discarded. If yields are low because of this it will add significantly to the cost.
All this means that the HMC is a very fast and power efficient product that is quite costly to manufacture. There has been no disclosure of how costly it is since it’s not yet in volume manufacture, but costs are expected to be high at the onset of production.
Now we get to a chicken-and-egg problem. Costs will doubtlessly undergo a significant decline once the HMC is manufactured in very high volume. Cost reduction is something the semiconductor market achieves with great finesse. But if the initial cost is high enough, the technology might never be adopted. Objective Analysis will take a “Wait and see” position on the HMC. Objective Analysis cannot say with any conviction whether or not a large market will develop for this technology.
Whether or not it achieves commercial success, the hybrid memory cube is an admirable piece of technology!
Objective Analysis has published a report on packaging technology for the cell phone business: Flash Packaging: What Phone Makers Want and Why which can be purchased for immediate download from the Objective Analysis website. Cadence’s Steve Leibson wrote an EDA360 Insider blog post with in-depth technical details about the Hybrid Memory Cube architecture for those who want to go down that path.
